High-speed ADC PCB layout techniques

In high-speed analog signal chain design, printed circuit board (PCB) layout requires consideration of many options. Some options are more important than others, and some options depend on the application. The final answer is different, but in all cases, the design engineer should try to eliminate the error of the best practice, not to over-calculate every detail of the layout and wiring. Here is an article written by Rob Reeder, an experienced system application engineer at ADI, "High Speed ​​ADC PCB Layout and Wiring Tips." An article written by Rob Reeder**** believes this article will be helpful to everyone's high-speed design projects. Exposed pad The exposed pad (EPAD) is sometimes overlooked, but it is very important for the performance of the signal chain and adequate heat dissipation of the device. The exposed pad, which Analog Devices calls pins 0, is the pad under most of today's devices. It is an important connection where all internal ground of the chip is connected to the center point below the device. I wonder if you have noticed that the lack of ground pins in many converters and amplifiers today is due to the exposed pad. The key is to properly secure (ie, solder) this pin to the PCB for reliable electrical and thermal connections. If this connection is not firm, there will be confusion. In other words, the design may not work. Make the best connection There are three steps to using the exposed pad to achieve the best electrical and thermal connections. First, if possible, the exposed pad should be replicated on each PCB layer. The purpose of this is to form a dense thermal connection with all ground and ground planes for rapid heat dissipation. This step is related to high power devices and applications with a high number of channels. Electrically, this will provide good equipotential bonding for all ground planes. It is even possible to replicate the exposed pad on the bottom layer (see Figure 1), which can be used as a decoupling heat sink ground and where the bottom side heat sink is mounted. Second, divide the exposed pad into multiple identical parts, like a chessboard. Use a screen cross grid on the exposed exposed pad, or use a solder mask. This step ensures a solid connection between the device and the PCB. In the reflow assembly process, it is impossible to determine how the solder paste flows and ultimately connect the device to the PCB. Connections may exist but are unevenly distributed. You may only get one connection, and the connection is small, or worse, at the corner. Dividing the exposed pad into smaller sections ensures that each area has a connection point for a more rugged, uniformly connected exposed pad (see Figure 2 and Figure 3). Finally, you should make sure that all parts have vias connected to ground. Each area is usually large enough to place multiple vias. Before assembly, be sure to fill each via with solder paste or epoxy resin. This step is very important to ensure that the exposed pad solder paste will not reflow into these via holes and affect proper connection. Finally, you should make sure that all parts have vias connected to ground. Each area is usually large enough to place multiple vias. Before assembly, be sure to fill each via with solder paste or epoxy resin. This step is very important to ensure that the exposed pad solder paste will not reflow into these via holes and affect proper connection. Decoupling and layer capacitance Sometimes engineers ignore the purpose of using decoupling, and only distribute a lot of capacitors of different sizes on the board, so that the lower impedance power supply is connected to ground. But the problem remains: how much capacitance is needed? Many related literature indicate that many capacitors of different sizes must be used to reduce the power transmission system (PDS) impedance, but this is not entirely correct. Conversely, simply selecting the correct size and type of capacitor can reduce the PDS impedance. Consider designing a 10 mΩ reference layer as shown in Figure 4. As the red curve shows, many different values ​​of capacitance are used on the system board, 0.001 μF, 0.01 μF, 0.1 μF, and so on. This of course can reduce the impedance in the 500 MHz frequency range, but look at the green curve. The same design uses only 0.1 μF and 10 μF capacitors. This proves that if you use the correct capacitor, you don't need so much capacitance. This also helps to save space and material (BOM) costs. Note that not all capacitors are [born equally", even if the same supplier has different processes, sizes, and styles. If the correct capacitor is not used, whether it is multiple capacitors or several different types, it will have a negative effect on the PDS. The result may be an inductive loop. Improper placement of capacitors or use of different processes and types of capacitors (and therefore different responses to the frequencies within the system) may cause resonances between each other (see Figure 5). It is important to understand the frequency response of the type of capacitor used by the system. The choice of capacitors will make it harder to design low-impedance PDS systems. PDS high-frequency layer capacitance To design a qualified PDS, you need to use a variety of capacitors (see Figure 4). The typical capacitance used on the PCB can only reduce the impedance of the DC or near-DC frequency to about 500 MHz. Above 500 MHz, the capacitance depends on the internal capacitance formed by the PCB. Note that close overlap of the power plane and ground plane will help. A PCB stack structure that supports larger layer capacitors should be designed. For example, a six-layer stack may include a top signal layer, a first ground plane, a first power plane, a second power plane, a second ground plane, and a bottom signal layer. It is specified that the first ground layer and the first power layer are close to each other in the stacked structure, and the two layers have a pitch of 2 to 4 mils to form a natural high-frequency layer capacitance. The biggest advantage of this capacitor is that it is free, just specify in the PCB manufacturing notes. If you have to split the power plane and there are multiple VDD power rails on the same layer, use as large a power plane as possible. Do not leave empty holes and pay attention to sensitive circuits. This will maximize the capacitance of the VDD layer. If the design allows additional layers (in the example above, from six to eight layers), two additional ground planes should be placed between the first and second power planes. In the case where the core pitch is also 2 to 3 mils, the intrinsic capacitance of the laminated structure will be doubled at this time (see Fig. 6 for an example). This structure is easier to design than adding more discrete high frequency capacitors to keep the impedance low at high frequencies. The task of the PDS is to minimize the voltage ripple generated in response to the supply current demand, which is important but often overlooked. All circuits need current, some circuits require more, and some circuits need to provide current at a faster rate. The use of fully decoupled, low-impedance power planes or ground planes, and good PCB stackups help minimize voltage ripple due to circuit current requirements. For example, depending on the decoupling strategy used, if the system design has a switching current of 1 A and the PDS impedance is 10 mΩ, the maximum voltage ripple is 10 mV. The calculation is simple: V = IR. With a perfect PCB stack, it can cover the high frequency range while using conventional decoupling around the power entry starting point and high power or inrush current devices to cover the low frequency range (